The present invention relates to a semiconductor memory device and, more particularly, to a technique effectively applicable to, for example, a bipolar CMOS type random access memory (hereinafter referred to as bipolar CMOS type RAM) composed of bipolar transistors, P-channel field effect transistors (MOSFETs), N-channel MOSFETs and so forth.
There is known a bipolar CMOS type RAM having an ECL (emitter coupled logic) interface so as to be interchangeable with an ECL circuit.
In such bipolar CMOS type RAM, its memory array comprises, for example, high resistance load type N-channel MOSFET memory cells (nMOS memory cells) including high resistance load elements and N-channel MOSFETs, while its peripheral circuit consists of a composite logic gate circuit (hereinafter referred to as bi-CMOS composite logic gate circuit) which is a combination of a bipolar transistor and a CMOS (complementary MOSFET), thereby realizing both a higher operation speed and a reduced power consumption.
Relative to such bipolar CMOS type M mentioned, there is proposed an improved method of minimizing the soft error rate while further expediting the write operation by the provision of, between each complementary data line and a high-level supply voltage of the circuit, a variable impedance load circuit is disposed which consists of a parallel connection of a first P-channel MOSFET kept normally in its on-state and a second P-channel MOSFET cut off selectively in the write operation.
With regard to the bipolar CMOS type RAM using variable impedance load circuits, a conventional example is disclosed in "Digest of Technical Papers", ISSCC (International Solid-State Circuits Conference) 1987, pp. 132-133.
FIG. 6 shows an exemplary configuration of a bipolar CMOS type RAM. In this diagram, the bipolar CMOS type RAM includes four memory mats MA1-MAT4 arranged to occupy the major central area of a semiconductor substrate SUB. Each of the memory mats MAT1-MAT4 comprises eight memory arrays and eight variable impedance load circuits LC1-LC8 disposed correspondingly to such memory arrays. Each of the load circuits LC1-LC8 comprises a first P-channel MOSFET so designed as to have a relatively small conductance and a second P-channel MOSFET so designed as to have a relatively large conductance and, in a write operation, cut off selectively in accordance with a corresponding selection timing signal sw11-sw18 or sw41-sw48. Each of the selection timing signals sw11-sw18 and sw41-sw48 is formed in a timing generator circuit TG by combining a predetermined address signal with a predetermined write control signal obtained in response to a write enable signal WE, and then is fed via a corresponding feed path to a corresponding variable impedance load circuit.